Doped polycide layers, i.e. composite layers of a doped silicon layer that is polycrystalline or amorphous and a metal silicide layer arranged thereon, are becoming more significant in LSI semiconductor circuits. For example, doped polycide layers are used in bipolar technology as terminal structures for emitters, bases and collectors and are used in CMOS technology as gate electrodes.
In the prior art, doped polycide layers are produced, among other things, applying a metal layer onto a doped silicon layer that is polycrystalline o amorphous that is arranged on a semiconductor substrate. With a temperature treatment, a part of the silicon layer reacts with the metal layer to form metal silicide. As a result, a dopant depletion of the remaining part of the silicon layer occurs. A reflow of dopant occurs from the silicon into the metal silicide. This effect is especially pronounced when boron is used as the dopant. The dopant depletion is explained on the basis of a parasitic metal-dopant reaction that occurs during the silicide formation and that leads to the formation of stable metal-dopant compounds such as, for example, TiB.sub.2.
The dopant depletion has extremely negative effects in what is referred to as the salicide process that is becoming more significant in CMOS technology. The simultaneous silication of a gate electrode and source/drain regions in the manufacture of MOS transistors is referred to as a salicide process. In this process, a metal, for example titanium, is deposited surface-wide on transistor regions that are already structured. Given a suitable temperature treatment, the silicide formation occurs on the exposed silicon surfaces, i.e. on the surface of a gate electrode of polysilicon or of amorphous silicon and o the substrate surface in the source/drain regions, the unreacted metal being preserved on regions masked with silicon oxide or silicon nitride. The metal and potential reaction products are selectively removed vis-a-vis the metal silicide by employing an appropriate etchant, so that the metal silicide remains only on the gate electrode and on the source/drain regions. A reduction in sheet and contact resistivities is achieved with this method and improves the transistor performance. The salicide process is described, for example, in an article by M. E. Alperin et al., IEEE Trans. Electron Devices, ED-32, 141 (1985).
The dopant depletion occurs both in the silicon electrode as well as in the source/drain regions in the salicide process. It therefore leads to increase source/drain contact resistances (see the article by A. Mitwalsky et al. , 6th International Symposium on Silicon Materials Science and Technology, ECS. Montreal, May 1990) and leads to the formation of a space-charge zone in the gate electrode. These effects reduce the saturation drain current which in turn leads to a loss of performance.
Since the dopant depletion is especially pronounced in the presence of boron, this effect particularly occurs for boron-doped or BF.sub.2 -doped gate electrodes and source/drain regions (see the articles by C. Y. Wong et al., Techn. Dig. IEDM 88, pages 238-241 (1988) and R. A. Chapman et al., Techn. Dig. IEDM 88, pages 52-55 (1988)). Gate electrodes of p.sup.+ -doped polycide and p-channel transistors are therefore particularly affected by the dopant depletion in the salicide process.
It is known from the literature in the prior art to suppress the dopant depletion by, for example, limiting the temperature parameters (see the article by H. Hayashida et al., Conf. Proc. VLSI Symp., pages 29-30 (1989)) or by reducing the silicide thickness (see the article by B. Davari et al., Techn. Dig. IEDM 88, pages 56-59 (1988)).
A reduction in the silicide thickness, however, has the disadvantage that it deteriorates both the conductivity in the gate electrode as well as the temperature stability of the silicide (see the article by R. Burmaster et al., Conf. Proc. ESDERC 89, pages 233-36, Springer-Verlag, 1989, edited by Hauberger, Ryssel, Lange).
The reduction in the temperature parameters leads to a significant limitation of the process management. This is especially disadvantageous since only slight improvements can be achieved by means of this measure.
The introduction of an intermediate layer acting as a diffusion barrier between the silicon layer and the metal silicide layer is possible for suppressing the dopant depletion. This, however, has the disadvantage of a noticeable increase in the complexity of the process and is limited to the gate electrode in the salicide process.